--- xc/lib/GL/mesa/src/drv/r200/r200_texstate.c.orig_4.3.99.9 Tue Aug 5 17:05:22 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_texstate.c Tue Aug 5 10:52:45 2003 @@ -1139,7 +1139,7 @@ cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK; cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */ cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */ - cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset; + cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset + rmesa->r200Screen->fbBase; cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; texobj->dirty_state &= ~(1<hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->r200Screen->depthOffset; + rmesa->r200Screen->depthOffset + rmesa->r200Screen->fbBase; rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = ((rmesa->r200Screen->depthPitch & @@ -385,8 +385,9 @@ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt; rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset & - R200_COLOROFFSET_MASK); + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + + rmesa->r200Screen->fbBase) + & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & R200_COLORPITCH_MASK) | @@ -442,6 +443,12 @@ #else R200_VC_NO_SWAP; #endif + + if(rmesa->r200Screen->chipset == R200_CHIPSET_RS300) { + /* Bypass TCL */ + rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); + } + rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = 0x100010; rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] = (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT); @@ -470,7 +477,7 @@ (R200_TXFORMAT_ST_ROUTE_STQ0 | (2 << R200_TXFORMAT_WIDTH_SHIFT) | (2 << R200_TXFORMAT_HEIGHT_SHIFT)); - rmesa->hw.tex[0].cmd[TEX_PP_TXOFFSET] = 0; + rmesa->hw.tex[0].cmd[TEX_PP_TXOFFSET] = rmesa->r200Screen->fbBase; rmesa->hw.tex[0].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[0].cmd[TEX_PP_TXFORMAT_X] = (/* R200_TEXCOORD_PROJ | */ @@ -505,7 +512,7 @@ (R200_TXFORMAT_ST_ROUTE_STQ1 | (2 << R200_TXFORMAT_WIDTH_SHIFT) | (2 << R200_TXFORMAT_HEIGHT_SHIFT)); - rmesa->hw.tex[1].cmd[TEX_PP_TXOFFSET] = 0; + rmesa->hw.tex[1].cmd[TEX_PP_TXOFFSET] = rmesa->r200Screen->fbBase; rmesa->hw.tex[1].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT_X] = (/* R200_TEXCOORD_PROJ | */ @@ -545,7 +552,10 @@ rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = (R200_VAP_TCL_ENABLE | (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)); - + /* + if(!(rmesa->TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)) + rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_TCL_ENABLE; + */ rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = (R200_VPORT_X_SCALE_ENA | R200_VPORT_Y_SCALE_ENA | --- xc/lib/GL/mesa/src/drv/r200/r200_context.c.orig_4.3.99.9 Tue Aug 5 17:06:44 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_context.c Tue Aug 5 10:52:45 2003 @@ -451,12 +451,13 @@ fprintf(stderr, "disabling 3D acceleration\n"); FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1); } - else if (getenv("R200_NO_TCL")) { + else if ((getenv("R200_NO_TCL")) || + (rmesa->r200Screen->chipset == R200_CHIPSET_RS300)) { fprintf(stderr, "disabling TCL support\n"); TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1); } else { - if (!getenv("R200_NO_VTXFMT")) { + if (!getenv("R200_NO_VTXFMT")) { r200VtxfmtInit( ctx ); } _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); --- xc/lib/GL/mesa/src/drv/r200/r200_texmem.c.orig_4.3.99.9 Tue Aug 5 17:05:14 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_texmem.c Tue Aug 5 10:52:45 2003 @@ -361,7 +361,7 @@ pitch, srcOffset, t->image[0].width * texFormat->TexelBytes, /* dst pitch! */ - t->bufAddr, + t->bufAddr + rmesa->r200Screen->fbBase, x, y, t->image[hwlevel].x + x, @@ -429,7 +429,7 @@ blit_format, texImage->RowStride * texFormat->TexelBytes, r200AgpOffsetFromVirtual( rmesa, texImage->Data ), - blit_pitch, t->bufAddr, + blit_pitch, t->bufAddr + rmesa->r200Screen->fbBase, 0, 0, 0, 0, width, height ); @@ -472,7 +472,7 @@ r200EmitBlit( rmesa, blit_format, blit_pitch, GET_START( ®ion ), - blit_pitch, t->bufAddr, + blit_pitch, t->bufAddr + rmesa->r200Screen->fbBase, 0, 0, 0, done, width, lines ); --- xc/lib/GL/mesa/src/drv/r200/r200_pixel.c.orig_4.3.99.9 Tue Aug 5 17:03:01 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_pixel.c Tue Aug 5 10:52:45 2003 @@ -217,7 +217,7 @@ { __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; int nbox = dPriv->numClipRects; - int src_offset = rmesa->state.color.drawOffset; + int src_offset = rmesa->state.color.drawOffset + rmesa->r200Screen->fbBase; int src_pitch = rmesa->state.color.drawPitch * rmesa->r200Screen->cpp; int dst_offset = r200AgpOffsetFromVirtual( rmesa, pixels); int dst_pitch = pitch * rmesa->r200Screen->cpp; @@ -356,7 +356,7 @@ blit_format, src_pitch, src_offset, rmesa->state.color.drawPitch * rmesa->r200Screen->cpp, - rmesa->state.color.drawOffset, + rmesa->state.color.drawOffset + rmesa->r200Screen->fbBase, bx - x, by - y, bx, by, bw, bh ); --- xc/lib/GL/mesa/src/drv/r200/r200_screen.h.orig_4.3.99.9 Tue Aug 5 17:04:10 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_screen.h Tue Aug 5 14:06:53 2003 @@ -51,6 +51,7 @@ #define R200_CHIPSET_R200 1 #define R200_CHIPSET_MOBILITY 2 +#define R200_CHIPSET_RS300 3 #define R200_NR_TEX_HEAPS 2 @@ -63,6 +64,7 @@ int AGPMode; unsigned int irq; /* IRQ number (0 means none) */ + unsigned int fbBase; unsigned int frontOffset; unsigned int frontPitch; unsigned int backOffset; --- xc/lib/GL/mesa/src/drv/r200/r200_ioctl.c.orig_4.3.99.9 Tue Aug 5 17:02:10 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_ioctl.c Tue Aug 5 10:52:45 2003 @@ -104,11 +104,11 @@ cmd.nbox = rmesa->numClipRects; cmd.boxes = (drmClipRect *)rmesa->pClipRects; } - + ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd) ); - + if (ret) fprintf(stderr, "drmCommandWrite: %d\n", ret); @@ -501,7 +501,7 @@ } R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset; + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset + rmesa->r200Screen->fbBase ; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } --- xc/lib/GL/mesa/src/drv/r200/r200_screen.c.orig_4.3.99.9 Tue Aug 5 17:03:43 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_screen.c Thu Aug 7 13:27:48 2003 @@ -38,6 +38,8 @@ #include "r200_screen.h" #include "r200_context.h" #include "r200_ioctl.h" +#include "radeon_reg.h" +#include "radeon_macros.h" /* for INREG() */ #include "mem.h" #include "context.h" @@ -55,6 +57,12 @@ #define PCI_CHIP_R200_LY 0x4C59 #define PCI_CHIP_R200_LZ 0x4C5A #define PCI_CHIP_RV200_QW 0x5157 + +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 + #endif static r200ScreenPtr __r200Screen; @@ -66,6 +74,7 @@ { r200ScreenPtr r200Screen; RADEONDRIPtr r200DRIPriv = (RADEONDRIPtr)sPriv->pDevPriv; + unsigned char *RADEONMMIO; /* Check the DRI version */ { @@ -125,6 +134,14 @@ __driUtilMessage("r200CreateScreen(): Device isn't an r200!\n"); FREE( r200Screen ); return NULL; + + case PCI_CHIP_RS300_5834: + case PCI_CHIP_RS300_5835: + case PCI_CHIP_RS300_5836: + case PCI_CHIP_RS300_5837: + r200Screen->chipset = R200_CHIPSET_RS300; + break; + default: r200Screen->chipset = R200_CHIPSET_R200; break; @@ -240,6 +257,9 @@ r200Screen->cpp = r200DRIPriv->bpp / 8; r200Screen->AGPMode = r200DRIPriv->AGPMode; + RADEONMMIO = r200Screen->mmio.map; + r200Screen->fbBase = (INREG(RADEON_MC_FB_LOCATION) & 0xffff) << 16; + r200Screen->frontOffset = r200DRIPriv->frontOffset; r200Screen->frontPitch = r200DRIPriv->frontPitch; r200Screen->backOffset = r200DRIPriv->backOffset; --- xc/lib/GL/mesa/src/drv/r200/r200_lock.c.orig_4.3.99.9 Tue Aug 5 17:02:34 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_lock.c Tue Aug 5 10:52:45 2003 @@ -63,7 +63,7 @@ } R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset; + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset + rmesa->r200Screen->fbBase; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } --- xc/lib/GL/mesa/src/drv/r200/r200_state.c.orig_4.3.99.9 Tue Aug 5 17:04:25 2003 +++ xc/lib/GL/mesa/src/drv/r200/r200_state.c Tue Aug 5 10:52:45 2003 @@ -1599,8 +1599,9 @@ } R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset & - R200_COLOROFFSET_MASK); + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + + rmesa->r200Screen->fbBase) + & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } --- xc/lib/GL/mesa/src/drv/radeon/radeon_screen.h.orig_4.3.99.9 Tue Aug 5 16:49:14 2003 +++ xc/lib/GL/mesa/src/drv/radeon/radeon_screen.h Tue Aug 5 16:12:07 2003 @@ -58,6 +58,7 @@ /* chipset features */ #define RADEON_CHIPSET_TCL (1 << 0) +#define RADEON_CHIPSET_IGP (1 << 1) typedef struct { @@ -67,6 +68,7 @@ int AGPMode; unsigned int irq; /* IRQ number (0 means none) */ + unsigned int fbBase; unsigned int frontOffset; unsigned int frontPitch; unsigned int backOffset; --- xc/lib/GL/mesa/src/drv/radeon/radeon_lock.c.orig_4.3.99.9 Tue Aug 5 16:56:15 2003 +++ xc/lib/GL/mesa/src/drv/radeon/radeon_lock.c Tue Aug 5 10:52:45 2003 @@ -74,7 +74,7 @@ } RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset; + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset+rmesa->radeonScreen->fbBase; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } --- xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c.orig_4.3.99.9 Tue Aug 5 16:55:50 2003 +++ xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c Tue Aug 5 10:52:45 2003 @@ -318,7 +318,7 @@ RADEON_DST_BLEND_GL_ZERO ); rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->radeonScreen->depthOffset; + rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbBase; rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = ((rmesa->radeonScreen->depthPitch & @@ -342,7 +342,7 @@ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset & + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset+rmesa->radeonScreen->fbBase) & RADEON_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & @@ -415,7 +415,7 @@ RADEON_TXFORMAT_ST_ROUTE_STQ0 | (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); - rmesa->hw.tex[0].cmd[TEX_PP_TXOFFSET] = 0x2000; + rmesa->hw.tex[0].cmd[TEX_PP_TXOFFSET] = 0x2000 + rmesa->radeonScreen->fbBase; rmesa->hw.tex[0].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[0].cmd[TEX_PP_TXCBLEND] = (RADEON_COLOR_ARG_A_ZERO | @@ -440,7 +440,7 @@ RADEON_TXFORMAT_ST_ROUTE_STQ1 | (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); - rmesa->hw.tex[1].cmd[TEX_PP_TXOFFSET] = 0x8000; + rmesa->hw.tex[1].cmd[TEX_PP_TXOFFSET] = 0x8000 + rmesa->radeonScreen->fbBase; rmesa->hw.tex[1].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[1].cmd[TEX_PP_TXCBLEND] = (RADEON_COLOR_ARG_A_ZERO | --- xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c.orig_4.3.99.9 Tue Aug 5 16:56:49 2003 +++ xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c Tue Aug 5 10:52:45 2003 @@ -1136,7 +1136,7 @@ cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK; - cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset; + cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset + rmesa->radeonScreen->fbBase; cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; texobj->dirty_state &= ~(1<pDevPriv; + unsigned char *RADEONMMIO; /* Check the DRI version */ { @@ -214,16 +223,26 @@ case PCI_CHIP_RV200_QW: case PCI_CHIP_RADEON_LW: radeonScreen->chipset |= RADEON_CHIPSET_TCL; + case PCI_CHIP_RS100_4136: + case PCI_CHIP_RS100_4336: + case PCI_CHIP_RS200_4137: + case PCI_CHIP_RS200_4337: + case PCI_CHIP_RS250_4237: + case PCI_CHIP_RS250_4437: + radeonScreen->chipset |= RADEON_CHIPSET_IGP; case PCI_CHIP_RADEON_QY: case PCI_CHIP_RADEON_QZ: case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: + break; } radeonScreen->cpp = radeonDRIPriv->bpp / 8; radeonScreen->AGPMode = radeonDRIPriv->AGPMode; + RADEONMMIO = radeonScreen->mmio.map; + radeonScreen->fbBase = (INREG(RADEON_MC_FB_LOCATION) & 0xffff) << 16; radeonScreen->frontOffset = radeonDRIPriv->frontOffset; radeonScreen->frontPitch = radeonDRIPriv->frontPitch; radeonScreen->backOffset = radeonDRIPriv->backOffset; --- xc/lib/GL/mesa/src/drv/radeon/radeon_context.c.orig_4.3.99.9 Tue Aug 5 16:55:02 2003 +++ xc/lib/GL/mesa/src/drv/radeon/radeon_context.c Wed Aug 6 15:02:00 2003 @@ -189,12 +189,17 @@ /* Initialize the extensions supported by this driver. */ -static void radeonInitExtensions( GLcontext *ctx ) +static void radeonInitExtensions( GLcontext *ctx, radeonScreenPtr radeonScreen) { unsigned i; _mesa_enable_imaging_extensions( ctx ); for ( i = 0 ; radeon_extensions[i] != NULL ; i++ ) { + if (radeonScreen->chipset & RADEON_CHIPSET_IGP) { + /* workaround multitexture problem for IGP chips, TODO: find the real cause + */ + if(!strcmp(radeon_extensions[i], "GL_ARB_multitexture")) continue; + } _mesa_enable_extension( ctx, radeon_extensions[i] ); } } @@ -404,7 +409,7 @@ _math_matrix_set_identity( &rmesa->TexGenMatrix[1] ); _math_matrix_set_identity( &rmesa->tmpmat ); - radeonInitExtensions( ctx ); + radeonInitExtensions( ctx, rmesa->radeonScreen ); radeonInitDriverFuncs( ctx ); radeonInitIoctlFuncs( ctx ); radeonInitStateFuncs( ctx ); --- xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c.orig_4.3.99.9 Wed Aug 13 20:34:08 2003 +++ xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c Tue Aug 5 10:52:45 2003 @@ -840,7 +840,7 @@ } RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset; + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset+rmesa->radeonScreen->fbBase; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } --- xc/lib/GL/mesa/src/drv/radeon/radeon_state.c.orig_4.3.99.9 Tue Aug 5 16:55:35 2003 +++ xc/lib/GL/mesa/src/drv/radeon/radeon_state.c Tue Aug 5 10:52:45 2003 @@ -1588,8 +1588,8 @@ } RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset & - RADEON_COLOROFFSET_MASK); + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset+rmesa->radeonScreen->fbBase) & + RADEON_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h.orig_4.3.99.9 Tue Aug 5 17:39:14 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h Wed Aug 6 11:01:37 2003 @@ -488,6 +488,7 @@ int depthX; int depthY; + int fbBase; int frontOffset; int frontPitch; int backOffset; @@ -569,6 +570,7 @@ extern void RADEONSelectBuffer(ScrnInfoPtr pScrn, int buffer); extern Bool RADEONAccelInit(ScreenPtr pScreen); +extern void RADEONAccelFallbackMMIO(ScreenPtr pScreen); extern void RADEONEngineInit(ScrnInfoPtr pScrn); extern Bool RADEONCursorInit(ScreenPtr pScreen); extern Bool RADEONDGAInit(ScreenPtr pScreen); --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h.orig_4.3.99.9 Tue Aug 5 18:31:43 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h Tue Aug 5 18:30:52 2003 @@ -73,6 +73,9 @@ # define RADEON_AGP_4X_MODE 0x04 # define RADEON_AGP_FW_MODE 0x10 # define RADEON_AGP_MODE_MASK 0x17 +# define RADEON_AGPv3_MODE 0x08 +# define RADEON_AGPv3_4X_MODE 0x01 +# define RADEON_AGPv3_8X_MODE 0x02 #define RADEON_ATTRDR 0x03c1 /* VGA */ #define RADEON_ATTRDW 0x03c0 /* VGA */ #define RADEON_ATTRX 0x03c0 /* VGA */ --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h.orig_4.3.99.9 Thu Aug 7 14:56:04 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h Thu Aug 7 14:57:20 2003 @@ -52,7 +52,7 @@ #define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */ -#define RADEON_AGP_MAX_MODE 4 +#define RADEON_AGP_MAX_MODE 8 #define RADEON_CARD_TYPE_RADEON 1 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c.orig_4.3.99.9 Tue Aug 5 17:38:59 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c Thu Aug 7 15:15:28 2003 @@ -705,6 +705,8 @@ if (info->ChipFamily < CHIP_FAMILY_R200) OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); + OUTREG(RADEON_AGP_CNTL, 0x20); + /* Modify the mode if the default mode * is not appropriate for this * particular combination of graphics @@ -716,10 +718,28 @@ device = drmAgpDeviceId(info->drmFD); mode &= ~RADEON_AGP_MODE_MASK; - switch (info->agpMode) { - case 4: mode |= RADEON_AGP_4X_MODE; - case 2: mode |= RADEON_AGP_2X_MODE; - case 1: default: mode |= RADEON_AGP_1X_MODE; + if ((mode & RADEON_AGPv3_MODE) && + (INREG(RADEON_AGP_STATUS) & RADEON_AGPv3_MODE)) { + switch (info->agpMode) { + case 8: mode |= RADEON_AGPv3_8X_MODE; + case 4: default: mode |= RADEON_AGPv3_4X_MODE; + } + /*TODO: need to take care of other bits valid for v3 mode + * currently these bits are not used in all tested cards. + */ + } else { + switch (info->agpMode) { + case 4: mode |= RADEON_AGP_4X_MODE; + case 2: mode |= RADEON_AGP_2X_MODE; + case 1: default: mode |= RADEON_AGP_1X_MODE; + } + if (info->IsIGP) { + /* Force to 4x mode, there are some problems with 1x + and 2x modes on AGP master side + */ + mode &= ~RADEON_AGP_MODE_MASK; + mode |= RADEON_AGP_4X_MODE; + } } if (info->agpFastWrite) mode |= RADEON_AGP_FW_MODE; @@ -764,7 +784,6 @@ drmAgpRelease(info->drmFD); return FALSE; } - /* Initialize the CP ring buffer data */ info->ringStart = info->agpOffset; info->ringMapSize = info->ringSize*1024*1024 + DRM_PAGE_SIZE; @@ -998,10 +1017,13 @@ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; int cpp = info->CurrentLayout.pixel_bytes; drmRadeonInit drmInfo; + unsigned char *RADEONMMIO = info->MMIO; + CARD32 tmp; memset(&drmInfo, 0, sizeof(drmRadeonInit)); if ((info->ChipFamily == CHIP_FAMILY_R200) || + (info->ChipFamily == CHIP_FAMILY_RS300) || (info->ChipFamily == CHIP_FAMILY_RV250) || (info->ChipFamily == CHIP_FAMILY_RV280) ) drmInfo.func = DRM_RADEON_INIT_R200_CP; @@ -1032,9 +1054,19 @@ drmInfo.buffers_offset = info->bufHandle; drmInfo.agp_textures_offset = info->agpTexHandle; + tmp = INREG(RADEON_MC_FB_LOCATION); if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT, &drmInfo, sizeof(drmRadeonInit)) < 0) return FALSE; + else if (info->fbBase != ((INREG(RADEON_MC_FB_LOCATION) & 0xffff) << 16)) { + /* This is to make sure we are not using a version of kernel driver with + the start of FB_LOCATION hard-coded to zero for IGP cards. + */ + xf86DrvMsg(pScreen->myNum, X_WARNING, + "Mismatched FB location. Incorrect version of DRM kernel driver is used.\n"); + OUTREG(RADEON_MC_FB_LOCATION, tmp); + return FALSE; + } /* DRM_RADEON_CP_INIT does an engine reset, which resets some engine * registers back to their default values, so we need to restore @@ -1222,7 +1254,8 @@ if (info->ChipFamily == CHIP_FAMILY_R200) pDRIInfo->clientDriverName = R200_DRIVER_NAME; else if ((info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280)) + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300)) pDRIInfo->clientDriverName = RV250_DRIVER_NAME; else pDRIInfo->clientDriverName = RADEON_DRIVER_NAME; @@ -1349,7 +1382,8 @@ if ((info->ChipFamily == CHIP_FAMILY_R200) || (info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280)) { + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300)) { req_minor = 5; req_patch = 0; } else { --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c.orig_4.3.99.9 Wed Aug 6 11:21:57 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c Wed Aug 6 11:26:44 2003 @@ -283,7 +283,7 @@ pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6; RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_DEFAULT_OFFSET, ((INREG(RADEON_DISPLAY_BASE_ADDR) >> 10) + OUTREG(RADEON_DEFAULT_OFFSET, ((info->fbBase >> 10) | (pitch64 << 22))); RADEONWaitForFifo(pScrn, 1); @@ -611,3 +611,13 @@ return TRUE; } + +/* This is used to let accel routines fallback to MMIO + * when DRI failed at DRIFinishScreenInit stage. + */ +void RADEONAccelFallbackMMIO(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONAccelInitMMIO(pScreen, info->accel); +} --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c.orig_4.3.99.9 Mon Aug 11 23:48:42 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c Thu Aug 7 14:54:21 2003 @@ -2008,10 +2008,13 @@ CARD32 tom = INREG(RADEON_NB_TOM); pScrn->videoRam = (((tom >> 16) - (tom & 0xffff) + 1) << 6); + OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); + info->fbBase = (tom & 0xffff) << 16; + OUTREG(RADEON_MC_FB_LOCATION, tom); - OUTREG(RADEON_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(RADEON_DISPLAY2_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(RADEON_OV0_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbBase); + OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbBase); + OUTREG(RADEON_OV0_BASE_ADDR, info->fbBase); /* This is supposed to fix the crtc2 noise problem. */ @@ -2028,9 +2031,10 @@ } } - else + else { pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; - + info->fbBase = 0; + } /* Some production boards of m6 will return 0 if it's 8 MB */ if (pScrn->videoRam == 0) pScrn->videoRam = 8192; @@ -3501,15 +3505,23 @@ info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; if (!info->IsPCI) { + unsigned char *RADEONMMIO = info->MMIO; if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &(info->agpMode))) { if (info->agpMode < 1 || info->agpMode > RADEON_AGP_MAX_MODE) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal AGP Mode: %d\n", info->agpMode); - return FALSE; + "Illegal AGP Mode: %dx, set to default %dx mode\n", + info->agpMode, RADEON_DEFAULT_AGP_MODE); + info->agpMode = RADEON_DEFAULT_AGP_MODE; } + + /* AGP_MAX_MODE is changed to allow v3 8x mode. + * At this time we don't know if the AGP bridge supports + * 8x mode. This will later be verified on both + * AGP master and target sides. + */ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "Using AGP %dx mode\n", info->agpMode); + "AGP %dx mode is configured\n", info->agpMode); } if ((info->agpFastWrite = xf86ReturnOptValBool(info->Options, @@ -4099,6 +4111,8 @@ (pScrn->displayWidth * pScrn->virtualY * info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); info->directRenderingEnabled = FALSE; + /* Allow DRI for test */ + /* } else if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200) || (info->ChipFamily == CHIP_FAMILY_RS300)) { @@ -4106,6 +4120,7 @@ xf86DrvMsg(scrnIndex, X_WARNING, "Direct rendering not yet supported on " "IGP320/330/340/350, 7000, 9000 integrated chips\n"); + */ } else if ((info->ChipFamily == CHIP_FAMILY_R300) || (info->ChipFamily == CHIP_FAMILY_R350) || (info->ChipFamily == CHIP_FAMILY_RV350)) { @@ -4364,15 +4379,15 @@ xf86DrvMsg(scrnIndex, X_INFO, "Will use %d kb for textures at offset 0x%x\n", info->textureSize/1024, info->textureOffset); - info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) | - (info->frontOffset >> 10)); + ((info->frontOffset+info->fbBase) >> 10)); info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) | - (info->backOffset >> 10)); + ((info->backOffset+info->fbBase) >> 10)); info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) | - (info->depthOffset >> 10)); + ((info->depthOffset+info->fbBase) >> 10)); + } else #endif { @@ -4514,6 +4529,8 @@ done their thing, complete the DRI setup. */ info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); + + if(!info->directRenderingEnabled) RADEONAccelFallbackMMIO(pScreen); } if (info->directRenderingEnabled) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); @@ -4820,6 +4837,7 @@ ~(RADEON_PLL_DIV_SEL)); if ((info->ChipFamily == CHIP_FAMILY_R300) || + (info->ChipFamily == CHIP_FAMILY_RS300) || (info->ChipFamily == CHIP_FAMILY_R350) || (info->ChipFamily == CHIP_FAMILY_RV350)) { if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c.orig_4.3.99.9 Tue Aug 5 17:39:51 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c Tue Aug 5 10:52:45 2003 @@ -181,8 +181,8 @@ pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6; - OUTREG(RADEON_DEFAULT_OFFSET, (((INREG(RADEON_DISPLAY_BASE_ADDR) + pScrn->fbOffset) >> 10) | - (pitch64 << 22))); + OUTREG(RADEON_DEFAULT_OFFSET, ((info->fbBase + pScrn->fbOffset) >> 10) | + (pitch64 << 22)); /* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */ --- xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h.orig_4.3.99.9 Tue Aug 5 17:50:36 2003 +++ xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drv.h Tue Aug 5 10:52:45 2003 @@ -125,6 +125,7 @@ drm_radeon_depth_clear_t depth_clear; + unsigned long fb_base; unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; --- xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_cp.c.orig_4.3.99.9 Tue Aug 5 17:49:36 2003 +++ xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_cp.c Tue Aug 5 20:20:57 2003 @@ -853,9 +853,10 @@ u32 ring_start, cur_read_ptr; u32 tmp; - /* Initialize the memory controller */ + /* Initialize the memory controller */ RADEON_WRITE( RADEON_MC_FB_LOCATION, - (dev_priv->agp_vm_start - 1) & 0xffff0000 ); + (dev_priv->agp_vm_start - 1) & 0xffff0000 | + (dev_priv->fb_base >> 16)); if ( !dev_priv->is_pci ) { RADEON_WRITE( RADEON_MC_AGP_LOCATION, @@ -884,6 +885,7 @@ cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); SET_RING_HEAD( dev_priv, cur_read_ptr ); + dev_priv->ring.tail = cur_read_ptr; #if __REALLY_HAVE_AGP @@ -924,6 +926,7 @@ RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); + /* Writeback doesn't seem to work everywhere, test it first */ DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); @@ -1047,13 +1050,6 @@ dev_priv->depth_offset = init->depth_offset; dev_priv->depth_pitch = init->depth_pitch; - dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | - (dev_priv->front_offset >> 10)); - dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | - (dev_priv->back_offset >> 10)); - dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) | - (dev_priv->depth_offset >> 10)); - /* Hardware state for depth clears. Remove this if/when we no * longer clear the depth buffer with a 3D rectangle. Hard-code * all values to prevent unwanted 3D state from slipping through @@ -1182,8 +1178,17 @@ } + dev_priv->fb_base = (RADEON_READ( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; + dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | + ((dev_priv->front_offset+dev_priv->fb_base) >> 10)); + dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | + ((dev_priv->back_offset+dev_priv->fb_base) >> 10)); + dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) | + ((dev_priv->depth_offset+dev_priv->fb_base) >> 10)); + dev_priv->agp_size = init->agp_size; - dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE ); + dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE ) + dev_priv->fb_base; + #if __REALLY_HAVE_AGP if ( !dev_priv->is_pci ) dev_priv->agp_buffers_offset = (dev_priv->buffers->offset --- xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c.orig_4.3.99.9 Tue Aug 5 17:49:53 2003 +++ xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_state.c Tue Aug 5 10:52:45 2003 @@ -153,7 +153,7 @@ OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); OUT_RING( tex[0].pp_txfilter ); OUT_RING( tex[0].pp_txformat ); - OUT_RING( tex[0].pp_txoffset ); + OUT_RING( tex[0].pp_txoffset + dev_priv->fb_base); OUT_RING( tex[0].pp_txcblend ); OUT_RING( tex[0].pp_txablend ); OUT_RING( tex[0].pp_tfactor ); @@ -167,7 +167,7 @@ OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); OUT_RING( tex[1].pp_txfilter ); OUT_RING( tex[1].pp_txformat ); - OUT_RING( tex[1].pp_txoffset ); + OUT_RING( tex[1].pp_txoffset + dev_priv->fb_base); OUT_RING( tex[1].pp_txcblend ); OUT_RING( tex[1].pp_txablend ); OUT_RING( tex[1].pp_tfactor ); @@ -181,7 +181,7 @@ OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); OUT_RING( tex[2].pp_txfilter ); OUT_RING( tex[2].pp_txformat ); - OUT_RING( tex[2].pp_txoffset ); + OUT_RING( tex[2].pp_txoffset + dev_priv->fb_base); OUT_RING( tex[2].pp_txcblend ); OUT_RING( tex[2].pp_txablend ); OUT_RING( tex[2].pp_tfactor ); @@ -932,7 +932,6 @@ (numverts << RADEON_NUM_VERTICES_SHIFT) ); ADVANCE_RING(); - i++; } while ( i < nbox ); } @@ -1008,14 +1007,6 @@ int start = prim->start + RADEON_INDEX_PRIM_OFFSET; int count = (prim->finish - start) / sizeof(u16); - DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", - prim->prim, - prim->vc_format, - prim->start, - prim->finish, - prim->offset, - prim->numverts); - if (bad_prim_vertex_nr( prim->prim, count )) { DRM_ERROR( "bad prim %x count %d\n", prim->prim, count ); @@ -1182,7 +1173,8 @@ RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); - buffer[2] = (tex->pitch << 22) | (tex->offset >> 10); + buffer[2] = ((tex->pitch << 22) | + ((tex->offset + dev_priv->fb_base) >> 10)); buffer[3] = 0xffffffff; buffer[4] = 0xffffffff; buffer[5] = (image->y << 16) | image->x; @@ -1817,7 +1809,7 @@ OUT_RING( CP_PACKET0( reg, (sz-1) ) ); OUT_RING_USER_TABLE( data, sz ); ADVANCE_RING(); - + cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; @@ -1840,6 +1832,7 @@ OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); OUT_RING_USER_TABLE( data, sz ); ADVANCE_RING(); + cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; @@ -1864,6 +1857,7 @@ OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); OUT_RING_USER_TABLE( data, sz ); ADVANCE_RING(); + cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; @@ -1972,11 +1966,11 @@ } radeon_emit_clip_rect( dev_priv, &box ); } - + BEGIN_RING( cmdsz ); OUT_RING_USER_TABLE( cmd, cmdsz ); ADVANCE_RING(); - + } while ( ++i < cmdbuf->nbox ); if (cmdbuf->nbox == 1) cmdbuf->nbox = 0;